Sun Fire 4800 系统平台管理(開機篇)

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      有些機器看似困難其實不然,經過一次操作後即可上手,主要困難的地方還是在於維護,但是操作的基礎奠定後之後,維護方面就容昜學習,下面我們將進入初步的教學,帶你如何使用SunFire 4800。

首先我們先看幾張圖學習部分安裝。

前面部分可安裝三顆POWER(啟動最少需要兩顆POWER)。

下方白色的為CONSOLE PORT1,4800需要另外的主機連入CONSOLE才能控制。
CPU板由左至右安裝。
再來電源的安裝;白色接頭的電源模組接頭接在主要最下方的POWER上,而左右為互相備援,
而最上方左右插孔各為機箱最上方風扇的接孔,由於這兩個接孔在主要電源開啟時就會通電,所以
建議接在機箱最上方的風扇為佳。
如要查看詳細安裝,請參考手冊Sun Fire 4800 系统安装指南.pdf
若要進一步管理及固障排除請參考Sun Fire 4800 系统平台管理手冊.pdf 
※上面兩個連結是一樣的(由於上傳大小超過限制使用GE作為替代。)
安裝後就要開始啟動POWER,啟動POWER的步驟為由下至上,關閉POWER的步驟為由上至下。

啟動完POWER我們就要開始啟動模組及電源

首先進入CONSOLE 9600 8 N 1

出現要你選Domain,poweron 要用sc mode 所以要選 ” 0 ” 

進入後鍵入poweron all

SunFire4800-sc0:SC> poweron all
PS0: powered on
PS1: powered on
RP0: powered on
RP2: powered on
/N0/SB0: powered on
/N0/IB6: powered on
/N0/IB8: powered on
如果沒有錯誤訊息則表示並無硬體問題。

再來鍵入console a 切換到Domain A

SunFire4800-sc0:SC> console a
Connected to Domain A
Domain Shell for Domain A
最後就是真正的開機了,鍵入setkeyswitch on
SunFire4800-sc0:A> setkeyswitch on
Powering boards on …
Testing CPU Boards …
{/N0/SB0/P0} Running CPU POR and Set Clocks
{/N0/SB0/P1} Running CPU POR and Set Clocks
{/N0/SB0/P2} Running CPU POR and Set Clocks
{/N0/SB0/P0} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P1} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P3} Running CPU POR and Set Clocks
{/N0/SB0/P2} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P3} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P2} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Subtest: Setting Fireplane Config Registers for aid 0x2
{/N0/SB0/P3} Subtest: Setting Fireplane Config Registers for aid 0x3
{/N0/SB0/P0} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P0} Subtest: Display CPU Version, frequency
{/N0/SB0/P1} Subtest: Display CPU Version, frequency
{/N0/SB0/P0} Version register = 003e0015.22000507
{/N0/SB0/P1} Version register = 003e0015.22000507
{/N0/SB0/P0} Running Basic CPU
{/N0/SB0/P1} Running Basic CPU
{/N0/SB0/P0} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P1} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P0} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P2} Running Basic CPU
{/N0/SB0/P1} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P3} Running Basic CPU
{/N0/SB0/P0} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Subtest: Display CPU Version, frequency
{/N0/SB0/P3} Subtest: Display CPU Version, frequency
{/N0/SB0/P2} Version register = 003e0015.22000507
{/N0/SB0/P3} Version register = 003e0015.22000507
{/N0/SB0/P2} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P3} Cpu/System ratio = 6, cpu actual frequency = 900
{/N0/SB0/P0} Subtest: I-Cache RAM Test
{/N0/SB0/P1} Subtest: I-Cache RAM Test
{/N0/SB0/P2} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P3} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P2} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Subtest: I-Cache RAM Test
{/N0/SB0/P3} Subtest: I-Cache RAM Test
{/N0/SB0/P0} Subtest: I-Cache TAGS Test
{/N0/SB0/P1} Subtest: I-Cache TAGS Test
{/N0/SB0/P2} Subtest: I-Cache TAGS Test
{/N0/SB0/P3} Subtest: I-Cache TAGS Test
{/N0/SB0/P0} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P1} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P2} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P3} Subtest: I-Cache Valid/Predict TAGS Test
{/N0/SB0/P0} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P1} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P2} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P3} Subtest: I-Cache Snoop Tags Test
{/N0/SB0/P0} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P1} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P2} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P3} Subtest: I-Cache Branch Predict Array Test
{/N0/SB0/P0} Subtest: I-Cache Initialization
{/N0/SB0/P1} Subtest: I-Cache Initialization
{/N0/SB0/P2} Subtest: I-Cache Initialization
{/N0/SB0/P3} Subtest: I-Cache Initialization
{/N0/SB0/P0} Subtest: D-Cache RAM Test
{/N0/SB0/P1} Subtest: D-Cache RAM Test
{/N0/SB0/P2} Subtest: D-Cache RAM Test
{/N0/SB0/P3} Subtest: D-Cache RAM Test
{/N0/SB0/P0} Subtest: D-Cache TAGS Test
{/N0/SB0/P1} Subtest: D-Cache TAGS Test
{/N0/SB0/P2} Subtest: D-Cache TAGS Test
{/N0/SB0/P3} Subtest: D-Cache TAGS Test
{/N0/SB0/P0} Subtest: D-Cache MicroTags Test
{/N0/SB0/P1} Subtest: D-Cache MicroTags Test
{/N0/SB0/P2} Subtest: D-Cache MicroTags Test
{/N0/SB0/P3} Subtest: D-Cache MicroTags Test
{/N0/SB0/P0} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P1} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P2} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P3} Subtest: D-Cache SnoopTags Test
{/N0/SB0/P0} Subtest: D-Cache Initialization
{/N0/SB0/P2} Subtest: D-Cache Initialization
{/N0/SB0/P1} Subtest: D-Cache Initialization
{/N0/SB0/P3} Subtest: D-Cache Initialization
{/N0/SB0/P0} Subtest: W-Cache RAM Test
{/N0/SB0/P1} Subtest: W-Cache RAM Test
{/N0/SB0/P2} Subtest: W-Cache RAM Test
{/N0/SB0/P3} Subtest: W-Cache RAM Test
{/N0/SB0/P0} Subtest: W-Cache TAGS Test
{/N0/SB0/P1} Subtest: W-Cache TAGS Test
{/N0/SB0/P2} Subtest: W-Cache TAGS Test
{/N0/SB0/P3} Subtest: W-Cache TAGS Test
{/N0/SB0/P0} Subtest: W-Cache Valid bit Test
{/N0/SB0/P1} Subtest: W-Cache Valid bit Test
{/N0/SB0/P2} Subtest: W-Cache Valid bit Test
{/N0/SB0/P3} Subtest: W-Cache Valid bit Test
{/N0/SB0/P0} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P1} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P2} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P3} Subtest: W-Cache Bank valid bit Test
{/N0/SB0/P0} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P1} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P2} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P3} Subtest: W-Cache SnoopTAGS Test
{/N0/SB0/P0} Subtest: W-Cache Initialization
{/N0/SB0/P1} Subtest: W-Cache Initialization
{/N0/SB0/P2} Subtest: W-Cache Initialization
{/N0/SB0/P3} Subtest: W-Cache Initialization
{/N0/SB0/P0} Subtest: P-Cache RAM Test
{/N0/SB0/P1} Subtest: P-Cache RAM Test
{/N0/SB0/P2} Subtest: P-Cache RAM Test
{/N0/SB0/P3} Subtest: P-Cache RAM Test
{/N0/SB0/P0} Subtest: P-Cache TAGS Test
{/N0/SB0/P1} Subtest: P-Cache TAGS Test
{/N0/SB0/P2} Subtest: P-Cache TAGS Test
{/N0/SB0/P3} Subtest: P-Cache TAGS Test
{/N0/SB0/P0} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P1} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P2} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P3} Subtest: P-Cache SnoopTags Test
{/N0/SB0/P0} Subtest: P-Cache Status Data Test
{/N0/SB0/P1} Subtest: P-Cache Status Data Test
{/N0/SB0/P2} Subtest: P-Cache Status Data Test
{/N0/SB0/P3} Subtest: P-Cache Status Data Test
{/N0/SB0/P0} Subtest: P-Cache Initialization
{/N0/SB0/P1} Subtest: P-Cache Initialization
{/N0/SB0/P2} Subtest: P-Cache Initialization
{/N0/SB0/P3} Subtest: P-Cache Initialization
{/N0/SB0/P0} Subtest: Branch Prediction Initialization
{/N0/SB0/P1} Subtest: Branch Prediction Initialization
{/N0/SB0/P2} Subtest: Branch Prediction Initialization
{/N0/SB0/P3} Subtest: Branch Prediction Initialization
{/N0/SB0/P0} Subtest: IMMU Registers Access
{/N0/SB0/P1} Subtest: IMMU Registers Access
{/N0/SB0/P2} Subtest: IMMU Registers Access
{/N0/SB0/P3} Subtest: IMMU Registers Access
{/N0/SB0/P0} Subtest: DMMU Registers Access
{/N0/SB0/P1} Subtest: DMMU Registers Access
{/N0/SB0/P2} Subtest: DMMU Registers Access
{/N0/SB0/P3} Subtest: DMMU Registers Access
{/N0/SB0/P0} Subtest: 4M DTLB RAM Test
{/N0/SB0/P1} Subtest: 4M DTLB RAM Test
{/N0/SB0/P2} Subtest: 4M DTLB RAM Test
{/N0/SB0/P3} Subtest: 4M DTLB RAM Test
{/N0/SB0/P0} Subtest: 8K DTLB RAM Test
{/N0/SB0/P1} Subtest: 8K DTLB RAM Test
{/N0/SB0/P2} Subtest: 8K DTLB RAM Test
{/N0/SB0/P3} Subtest: 8K DTLB RAM Test
{/N0/SB0/P0} Subtest: 4M DTLB TAG Test
{/N0/SB0/P1} Subtest: 4M DTLB TAG Test
{/N0/SB0/P2} Subtest: 4M DTLB TAG Test
{/N0/SB0/P0} Subtest: 8K DTLB TAG Test
{/N0/SB0/P1} Subtest: 8K DTLB TAG Test
{/N0/SB0/P2} Subtest: 8K DTLB TAG Test
{/N0/SB0/P3} Subtest: 4M DTLB TAG Test
{/N0/SB0/P0} Subtest: 4M ITLB RAM Test
{/N0/SB0/P1} Subtest: 4M ITLB RAM Test
{/N0/SB0/P2} Subtest: 4M ITLB RAM Test
{/N0/SB0/P3} Subtest: 8K DTLB TAG Test
{/N0/SB0/P0} Subtest: 8K ITLB RAM Test
{/N0/SB0/P1} Subtest: 8K ITLB RAM Test
{/N0/SB0/P2} Subtest: 8K ITLB RAM Test
{/N0/SB0/P3} Subtest: 4M ITLB RAM Test
{/N0/SB0/P0} Subtest: 4M ITLB TAG Test
{/N0/SB0/P1} Subtest: 4M ITLB TAG Test
{/N0/SB0/P2} Subtest: 4M ITLB TAG Test
{/N0/SB0/P3} Subtest: 8K ITLB RAM Test
{/N0/SB0/P0} Subtest: 8K ITLB TAG Test
{/N0/SB0/P1} Subtest: 8K ITLB TAG Test
{/N0/SB0/P2} Subtest: 8K ITLB TAG Test
{/N0/SB0/P3} Subtest: 4M ITLB TAG Test
{/N0/SB0/P0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P2} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3} Subtest: 8K ITLB TAG Test
{/N0/SB0/P0} Subtest: E-Cache TAGS Test
{/N0/SB0/P1} Subtest: E-Cache TAGS Test
{/N0/SB0/P2} Subtest: E-Cache TAGS Test
{/N0/SB0/P3} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3} Subtest: E-Cache TAGS Test
{/N0/SB0/P0} Subtest: Fast Init. Verification Test
{/N0/SB0/P1} Subtest: Fast Init. Verification Test
{/N0/SB0/P2} Subtest: Fast Init. Verification Test
{/N0/SB0/P3} Subtest: Fast Init. Verification Test
{/N0/SB0/P0} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P1} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P2} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P3} Subtest: E-Cache TAGS ECC Test
{/N0/SB0/P2} Running Enable MMU
{/N0/SB0/P3} Running Enable MMU
{/N0/SB0/P2} Subtest: IMMU Initialization
{/N0/SB0/P3} Subtest: IMMU Initialization
{/N0/SB0/P0} Running Enable MMU
{/N0/SB0/P2} Subtest: DMMU Initialization
{/N0/SB0/P1} Running Enable MMU
{/N0/SB0/P3} Subtest: DMMU Initialization
{/N0/SB0/P2} Subtest: Map LPOST to local space
{/N0/SB0/P3} Subtest: Map LPOST to local space
{/N0/SB0/P0} Subtest: IMMU Initialization
{/N0/SB0/P1} Subtest: IMMU Initialization
{/N0/SB0/P0} Subtest: DMMU Initialization
{/N0/SB0/P1} Subtest: DMMU Initialization
{/N0/SB0/P0} Subtest: Map LPOST to local space
{/N0/SB0/P1} Subtest: Map LPOST to local space
{/N0/SB0/P0} Running FPU Tests
{/N0/SB0/P2} Running FPU Tests
{/N0/SB0/P1} Running FPU Tests
{/N0/SB0/P0} Subtest: FPU Register Test
{/N0/SB0/P1} Subtest: FPU Register Test
{/N0/SB0/P3} Running FPU Tests
{/N0/SB0/P2} Subtest: FPU Register Test
{/N0/SB0/P3} Subtest: FPU Register Test
{/N0/SB0/P0} Subtest: FSR Test
{/N0/SB0/P1} Subtest: FSR Test
{/N0/SB0/P2} Subtest: FSR Test
{/N0/SB0/P3} Subtest: FSR Test
{/N0/SB0/P2} Running Basic Ecache
{/N0/SB0/P3} Running Basic Ecache
{/N0/SB0/P0} Running Basic Ecache
{/N0/SB0/P2} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P3} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P1} Running Basic Ecache
{/N0/SB0/P0} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P1} Subtest: E-Cache Quick Verification Test
{/N0/SB0/P2} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P0} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P3} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P1} Subtest: E-Cache RAM Test Part1
{/N0/SB0/P2} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P3} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P0} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P1} Subtest: E-Cache RAM Test Part2
{/N0/SB0/P2} Subtest: E-Cache Address Line Test
{/N0/SB0/P0} Subtest: E-Cache Address Line Test
{/N0/SB0/P3} Subtest: E-Cache Address Line Test
{/N0/SB0/P1} Subtest: E-Cache Address Line Test
{/N0/SB0/P2} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P2} Subtest: E-Cache Initialization
{/N0/SB0/P0} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Subtest: E-Cache Initialization
{/N0/SB0/P0} Subtest: E-Cache Initialization
{/N0/SB0/P1} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P1} Subtest: E-Cache Initialization
{/N0/SB0/P0} Running Memory Configuration Tests
{/N0/SB0/P2} Running Memory Configuration Tests
{/N0/SB0/P1} Running Memory Configuration Tests
{/N0/SB0/P3} Running Memory Configuration Tests
{/N0/SB0/P0} Subtest: Disable Memory Controllers
{/N0/SB0/P2} Subtest: Disable Memory Controllers
{/N0/SB0/P1} Subtest: Disable Memory Controllers
{/N0/SB0/P3} Subtest: Disable Memory Controllers
{/N0/SB0/P2} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P0} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P1} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P3} Subtest: Mem Addr Control Reg Test
{/N0/SB0/P0} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P1} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P2} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P3} Subtest: Mem Addr Decoding Reg Test
{/N0/SB0/P0} Subtest: Memory Controller Configuration
{/N0/SB0/P1} Subtest: Memory Controller Configuration
{/N0/SB0/P2} Subtest: Memory Controller Configuration
{/N0/SB0/P3} Subtest: Memory Controller Configuration
{/N0/SB0/P0} Subtest: UP Memory Clear
{/N0/SB0/P2} Subtest: UP Memory Clear
{/N0/SB0/P1} Subtest: UP Memory Clear
{/N0/SB0/P3} Subtest: UP Memory Clear
{/N0/SB0/P0} Running Memory Tests
{/N0/SB0/P1} Running Memory Tests
{/N0/SB0/P2} Running Memory Tests
{/N0/SB0/P0} Subtest: Memory Addressing
{/N0/SB0/P3} Running Memory Tests
{/N0/SB0/P1} Subtest: Memory Addressing
{/N0/SB0/P2} Subtest: Memory Addressing
{/N0/SB0/P3} Subtest: Memory Addressing
{/N0/SB0/P0} Subtest: Memory DIMM Access
{/N0/SB0/P1} Subtest: Memory DIMM Access
{/N0/SB0/P2} Subtest: Memory DIMM Access
{/N0/SB0/P3} Subtest: Memory DIMM Access
{/N0/SB0/P0} Subtest: Memory MATS+
{/N0/SB0/P1} Subtest: Memory MATS+
{/N0/SB0/P2} Subtest: Memory MATS+
{/N0/SB0/P3} Subtest: Memory MATS+
{/N0/SB0/P2} Subtest: Memory MARCH C-
{/N0/SB0/P3} Subtest: Memory MARCH C-
{/N0/SB0/P2} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P3} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P0} Subtest: Memory MARCH C-
{/N0/SB0/P1} Subtest: Memory MARCH C-
{/N0/SB0/P0} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P1} Subtest: Memory Alternating Multiple Access Selection
{/N0/SB0/P0} Running Ecache Functional
{/N0/SB0/P1} Running Ecache Functional
{/N0/SB0/P0} Subtest: E-Cache Functional
{/N0/SB0/P1} Subtest: E-Cache Functional
{/N0/SB0/P2} Running Ecache Functional
{/N0/SB0/P3} Running Ecache Functional
{/N0/SB0/P0} Subtest: E-Cache Stress
{/N0/SB0/P1} Subtest: E-Cache Stress
{/N0/SB0/P2} Subtest: E-Cache Functional
{/N0/SB0/P3} Subtest: E-Cache Functional
{/N0/SB0/P2} Subtest: E-Cache Stress
{/N0/SB0/P3} Subtest: E-Cache Stress
{/N0/SB0/P2} Running CPU Functional
{/N0/SB0/P3} Running CPU Functional
{/N0/SB0/P2} Subtest: IMMU Functional
{/N0/SB0/P3} Subtest: IMMU Functional
{/N0/SB0/P2} Subtest: DMMU Functional
{/N0/SB0/P3} Subtest: DMMU Functional
{/N0/SB0/P0} Running CPU Functional
{/N0/SB0/P1} Running CPU Functional
{/N0/SB0/P0} Subtest: IMMU Functional
{/N0/SB0/P1} Subtest: IMMU Functional
{/N0/SB0/P2} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P3} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P0} Subtest: DMMU Functional
{/N0/SB0/P1} Subtest: DMMU Functional
{/N0/SB0/P0} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P1} Subtest: Dual AFSR/AFAR First Error Capture Test
{/N0/SB0/P2} Subtest: I-Cache Functional
{/N0/SB0/P3} Subtest: I-Cache Functional
{/N0/SB0/P0} Subtest: I-Cache Functional
{/N0/SB0/P1} Subtest: I-Cache Functional
{/N0/SB0/P2} Subtest: I-Cache Parity Functional
{/N0/SB0/P3} Subtest: I-Cache Parity Functional
{/N0/SB0/P0} Subtest: I-Cache Parity Functional
{/N0/SB0/P1} Subtest: I-Cache Parity Functional
{/N0/SB0/P2} Subtest: I-Cache Parity Tag
{/N0/SB0/P3} Subtest: I-Cache Parity Tag
{/N0/SB0/P0} Subtest: I-Cache Parity Tag
{/N0/SB0/P1} Subtest: I-Cache Parity Tag
{/N0/SB0/P2} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P3} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P0} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P1} Subtest: I-Cache Snoop Parity Tag
{/N0/SB0/P2} Subtest: D-Cache Functional
{/N0/SB0/P3} Subtest: D-Cache Functional
{/N0/SB0/P0} Subtest: D-Cache Functional
{/N0/SB0/P1} Subtest: D-Cache Functional
{/N0/SB0/P2} Subtest: D-Cache Parity Functional
{/N0/SB0/P3} Subtest: D-Cache Parity Functional
{/N0/SB0/P0} Subtest: D-Cache Parity Functional
{/N0/SB0/P1} Subtest: D-Cache Parity Functional
{/N0/SB0/P2} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P3} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P0} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P1} Subtest: D-Cache Parity Tag Test
{/N0/SB0/P2} Subtest: W-Cache Functional
{/N0/SB0/P3} Subtest: W-Cache Functional
{/N0/SB0/P2} Subtest: P-Cache Functional
{/N0/SB0/P3} Subtest: P-Cache Functional
{/N0/SB0/P0} Subtest: W-Cache Functional
{/N0/SB0/P1} Subtest: W-Cache Functional
{/N0/SB0/P2} Subtest: FPU Functional
{/N0/SB0/P3} Subtest: FPU Functional
{/N0/SB0/P0} Subtest: P-Cache Functional
{/N0/SB0/P1} Subtest: P-Cache Functional
{/N0/SB0/P0} Subtest: FPU Functional
{/N0/SB0/P1} Subtest: FPU Functional
{/N0/SB0/P2} Subtest: Graphics Functional
{/N0/SB0/P3} Subtest: Graphics Functional
{/N0/SB0/P0} Subtest: Graphics Functional
{/N0/SB0/P1} Subtest: Graphics Functional
{/N0/SB0/P0} Running Advanced CPU Tests
{/N0/SB0/P1} Running Advanced CPU Tests
{/N0/SB0/P0} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P1} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P2} Running Advanced CPU Tests
{/N0/SB0/P3} Running Advanced CPU Tests
{/N0/SB0/P2} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P3} Subtest: CPU Superscalar Dispatch
{/N0/SB0/P0} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P1} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P0} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P1} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P2} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P3} Subtest: SPARC Atomic Instruction Test
{/N0/SB0/P0} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P1} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P2} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P0} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P3} Subtest: Non SPARC Atomic Instruction Test
{/N0/SB0/P1} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P2} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P3} Subtest: SOFTINT Register and Interrupt Test
{/N0/SB0/P0} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P1} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P2} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P3} Subtest: CPU Tick and Tick Compare Registers Test
{/N0/SB0/P0} Subtest: FPU Move to Registers Test
{/N0/SB0/P1} Subtest: FPU Move to Registers Test
{/N0/SB0/P2} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P3} Subtest: CPU Stick and Stick Compare Registers Test
{/N0/SB0/P0} Subtest: FPU Branch Test
{/N0/SB0/P1} Subtest: FPU Branch Test
{/N0/SB0/P2} Subtest: FPU Move to Registers Test
{/N0/SB0/P3} Subtest: FPU Move to Registers Test
{/N0/SB0/P0} Subtest: Branch Memory Test
{/N0/SB0/P1} Subtest: Branch Memory Test
{/N0/SB0/P2} Subtest: FPU Branch Test
{/N0/SB0/P3} Subtest: FPU Branch Test
{/N0/SB0/P2} Subtest: Branch Memory Test
{/N0/SB0/P3} Subtest: Branch Memory Test
{/N0/SB0/P2} Running CPU ECC Tests
{/N0/SB0/P3} Running CPU ECC Tests
{/N0/SB0/P2} Subtest: Fast ECC errors test
{/N0/SB0/P3} Subtest: Fast ECC errors test
{/N0/SB0/P0} Running CPU ECC Tests
{/N0/SB0/P1} Running CPU ECC Tests
{/N0/SB0/P0} Subtest: Fast ECC errors test
{/N0/SB0/P1} Subtest: Fast ECC errors test
{/N0/SB0/P2} Subtest: MTAG ECC errors test
{/N0/SB0/P3} Subtest: MTAG ECC errors test
{/N0/SB0/P2} Subtest: SYSTEM ECC errors test
{/N0/SB0/P3} Subtest: SYSTEM ECC errors test
{/N0/SB0/P0} Subtest: MTAG ECC errors test
{/N0/SB0/P1} Subtest: MTAG ECC errors test
{/N0/SB0/P0} Subtest: SYSTEM ECC errors test
{/N0/SB0/P1} Subtest: SYSTEM ECC errors test
{/N0/SB0/P2} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P3} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P0} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P1} Subtest: Ecache Tag ECC errors test
{/N0/SB0/P0} Running System Level Tests
{/N0/SB0/P1} Running System Level Tests
{/N0/SB0/P0} Subtest: MP Memory Access Test
{/N0/SB0/P1} Subtest: MP Memory Access Test
{/N0/SB0/P2} Running System Level Tests
{/N0/SB0/P3} Running System Level Tests
{/N0/SB0/P2} Subtest: MP Memory Access Test
{/N0/SB0/P3} Subtest: MP Memory Access Test
{/N0/SB0/P0} Running Board Memory Interleave
{/N0/SB0/P1} Running Board Memory Interleave
{/N0/SB0/P0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P1} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P2} Running Board Memory Interleave
{/N0/SB0/P3} Running Board Memory Interleave
{/N0/SB0/P2} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P3} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P0} Passed
{/N0/SB0/P1} Passed
{/N0/SB0/P2} Passed
{/N0/SB0/P3} Passed
Testing IO Boards …
Loading the test table from board IB6 PROM 0 …
Copying IO PROM to CPU DRAM
……………………………………..
{/N0/SB0/P0} Running PCI IO Controller Basic Tests
{/N0/SB0/P0} Jumping to memory 00000000.00000020 [00000010]
{/N0/SB0/P0} System PCI IO post code running from memory
{/N0/SB0/P0} @(#) lpost         5.20.2  2006/08/22 14:12
{/N0/SB0/P0} Running PCI IO Controller Functional Tests
{/N0/SB0/P0} Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P0} Subtest: PCI IO Controller Register Initialization for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller IOMMU  TLB Compare Tests for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller IOMMU TLB Flush Tests for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller DMA loopback Tests for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller block DMA loopback Tests for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller Interrupt Tests for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller MergeBuffer Tests for aid 0x18
{/N0/SB0/P0} Subtest: PCI IO Controller StreamCache Tests for aid 0x18
{/N0/SB0/P0} Subtest: Schizo clean up for aid 0x18
{/N0/SB0/P0} Running PCI IO Controller Ecc Tests
{/N0/SB0/P0} Subtest: PCI IO Controller ECC Tests for aid 0x18
{/N0/SB0/P0} Subtest: Schizo clean up for aid 0x18
{/N0/SB0/P0} Running SBBC Basic Tests
{/N0/SB0/P0} Subtest: SBBC PCI Reg Initialization for aid 0x18
{/N0/SB0/P0} Running Probe io Devices
{/N0/SB0/P0} Running PCI IO Controller Basic Tests
{/N0/SB0/P0} Subtest: PCI IO Controller Register Initialization for aid 0x19
{/N0/SB0/P0} Running PCI IO Controller Functional Tests
{/N0/SB0/P0} Subtest: PCI IO Controller IOMMU  TLB Compare Tests for aid 0x19
{/N0/SB0/P0} Subtest: PCI IO Controller IOMMU TLB Flush Tests for aid 0x19
{/N0/SB0/P0} Subtest: PCI IO Controller DMA loopback Tests for aid 0x19
{/N0/SB0/P0} Subtest: PCI IO Controller block DMA loopback Tests for aid 0x19
{/N0/SB0/P0} Subtest: PCI IO Controller Interrupt Tests for aid 0x19
{/N0/SB0/P0} Running PCI IO Controller Ecc Tests
{/N0/SB0/P0} Subtest: PCI IO Controller MergeBuffer Tests for aid 0x19
{/N0/SB0/P0} Subtest: PCI IO Controller StreamCache Tests for aid 0x19
{/N0/SB0/P0} Subtest: Schizo clean up for aid 0x19
{/N0/SB0/P0} Subtest: PCI IO Controller ECC Tests for aid 0x19
{/N0/SB0/P0} Running Probe io Devices
{/N0/SB0/P0} Subtest: Schizo clean up for aid 0x19
{/N0/SB0/P0} @(#) lpost         5.13.2  2002/06/21 12:33
{/N0/SB0/P0} Copyright 2001 Sun Microsystems, Inc. All rights reserved.
{/N0/IB6/P0} Passed
{/N0/IB6/P1} Passed
Testing domain …
{/N0/SB0/P0} Running Domain Level Tests
{/N0/SB0/P0} Subtest: Mapping IO SRAM
{/N0/SB0/P0} Subtest: Memory interleaving config
{/N0/SB0/P0} Running Domain Basic Tests
{/N0/SB0/P0} Subtest: Cross Call Test
{/N0/SB0/P0} Running Domain Advanced Tests
{/N0/SB0/P0} Subtest: MP Memory Clear Test
{/N0/SB0/P0}  CPU 1 clearing 00000000.00000000 to 00000001.00000000
{/N0/SB0/P0}  CPU 2 clearing 00000001.00000000 to 00000002.00000000
{/N0/SB0/P0}  CPU 3 clearing 00000002.00000000 to 00000003.00000000
{/N0/SB0/P0}  CPU 0 clearing 00000003.00000000 to 00000004.00000000
{/N0/SB0/P0} Subtest: DCache Snoop Tag Parity Test
{/N0/SB0/P0} Subtest: MP Cache Coherency Test
{/N0/SB0/P0} Subtest: Memory Controller Saturation Test
{/N0/SB0/P0}    All CPUs saturate /SB0/P0’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P1’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P2’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P3’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P0’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P1’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P2’s memory controller
{/N0/SB0/P0}    All CPUs saturate /SB0/P3’s memory controller
{/N0/SB0/P0} Subtest: Fireplane Bus Saturation Test
{/N0/SB0/P0} Subtest: MP Memory Clear Test
{/N0/SB0/P0}  CPU 1 clearing 00000000.00000000 to 00000001.00000000
{/N0/SB0/P0}  CPU 2 clearing 00000001.00000000 to 00000002.00000000
{/N0/SB0/P0}  CPU 3 clearing 00000002.00000000 to 00000003.00000000
{/N0/SB0/P0}  CPU 0 clearing 00000003.00000000 to 00000004.00000000
{/N0/SB0/P0} Running Domain Stick Sync Tests
{/N0/SB0/P0} Subtest: Sync. Stick Registers Test
{/N0/SB0/P0} Running Domain Verify Stick Sync Tests
{/N0/SB0/P0} Subtest: Verify Sync. Stick Registers Test
{/N0/SB0/P0}  DCB_DECOMP_OBP command succeeded
{/N0/SB0/P0} Decompress OBP done
{/N0/SB0/P0}  DCB_ENTER_OBP  command succeeded
{/N0/SB0/P1}  DCB_ENTER_OBP  command succeeded
{/N0/SB0/P2}  DCB_ENTER_OBP  command succeeded
{/N0/SB0/P3}  DCB_ENTER_OBP  command succeeded
Entering OBP …
Sun Fire 4800
OpenFirmware version 5.13.2 (06/21/02 12:33)
Copyright 2001 Sun Microsystems, Inc.  All rights reserved.
SmartFirmware, Copyright (C) 1996-2001.  All rights reserved.
16384 MB memory installed, Serial #52731247.
Ethernet address 0:3:ba:24:9d:6f, Host ID: 83249d6f.
WARNING: Find no network devices.
WARNING: Find no block devices, e.g. disks, CD-ROM, etc.
ERROR: No usable device to boot Solaris!
ERROR: Can’t open boot-device
{0} ok

到了ok mode 表示已經開機了,當然能見到ok也表示整台機器是沒有問題的。

附件上傳者:onizka

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